1. Field of the Invention
The present invention relates, in general, to test systems for testing circuits having a number of circuit subunits or chips in a multichip housing. The present invention relates, in particular, to a test apparatus in which a test system is connected to the circuit unit to be tested, it being possible to test the circuit subunits which are associated with the circuit unit to be tested without having to provide an increased number of connection pins.
2. Description of the Related Art
The present invention relates specifically to a test apparatus for testing a circuit unit which is to be tested and has circuit subunits, said test apparatus having a test system for outputting test signals to the circuit unit to be tested and for evaluating response signals which are output from the circuit unit to be tested on the basis of the test signals supplied to the latter, a tester channel for connecting the circuit unit to be tested to the test system, and a connecting unit which is intended to connect the tester channel to the circuit subunits of the circuit unit to be tested.
In large-scale integrated circuit units, for example integrated memory circuits (dies), which are provided as a module in the form of a so-called multichip housing (multichip package, MCP), it must be possible to test the overall module after it has been housed. The final test is extremely complex since circuit subunits having very different functionalities and test requirements are typically combined in an MCP.
There is thus the disadvantage that a large number of external contacts need to be provided in order to connect the test system to the different circuit subunits of a circuit unit which is to be tested and is designed as a multichip package.
Such a large number of connecting contacts inexpediently requires a correspondingly large number of contacts on the test system. This results in the disadvantage that the number of circuit units which can be tested in parallel is reduced. This results in the test costs being increased and/or in the test time being extended. Another disadvantage of conventional test methods resides in the fact that no standard set of test functionalities can be provided since the circuit subunits in a multichip housing may be fabricated by different semiconductor manufacturers.